Design of Decoder Architecture on Semi-Algebra Low-Density Parity-Check Codes

Recently, Low-Density Parity-Check (LDPC) codes have attracted much attention because of their excellent error-correcting performance and highly parallelizable decoding scheme. However, main drawbacks of LDPC codes such as the higher encoding complexity and short cycles in the Tanner graph that result in difficulties of hardware implementation and poor performance with the iterative decoding algorithm. In this paper two main have been done, one work is that the construction of Semi-Algebra Low-Density Parity-Check codes with an arbitrary block length is presented, the other work is that efficient parallel VLSI decoder implementations on the SA-LDPC. The proposed works have significantly reduced the memory requirements and the interconnect complexity and also improves decoding throughputs.